AD7690 datasheet(15/29 Pages) AD

15 / 29 page

AD7903

Data Sheet

Rev. A | Page 14 of 28

THEORY OF OPERATION

Figure 31. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7903 is a fast, low power, precise, dual 16-bit ADC

using a successive approximation architecture.

The AD7903 is capable of simultaneously converting 1,000,000

samples per second (1 MSPS) and powers down between con-

versions. When operating at 10 kSPS, for example, it typically

consumes 70 µW per ADC, making it ideal for battery-powered

applications.

The AD7903 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multichannel multiplexed applications.

The AD7903 can be interfaced to any 1.8 V to 5 V digital logic

family. It is available in a 20-lead QSOP that allows flexible

configurations.

The device is pin-for-pin compatible with the pseudo differential,

16-bit AD7902.

CONVERTER OPERATION

The AD7903 is a dual successive approximation ADC based on

a charge redistribution DAC. Figure 31 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase of each ADC, terminals of the

array tied to the input of the comparator are connected to GND

via SWx+ and SWx−. All independent switches are connected

to the analog inputs. Therefore, the capacitor arrays are used as

sampling capacitors and acquire the analog signal on the INx+

and INx− inputs. When the acquisition phase is complete and

the CNVx input goes high, a conversion phase is initiated. When

the conversion phase begins, SWx+ and SWx− are opened first.

The two capacitor arrays are then disconnected from the inputs

and connected to the GND input. Therefore, the differential

voltage between the INx+ and INx− inputs, captured at the end

of the acquisition phase, is applied to the comparator inputs,

causing the comparator to become unbalanced. By switching

each element of the capacitor array between GND and REFx,

the comparator input varies by binary-weighted voltage steps

(VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

into a balanced condition. After the completion of this process,

the part returns to the acquisition phase, and the control logic

generates the ADC output code and a busy signal indicator.

Because the AD7903 has an on-board conversion clock, the

serial clock, SCKx, is not required for the conversion process.

Transfer Functions

The ideal transfer characteristic for the AD7903 is shown in

Figure 32 and Table 7.

Figure 32. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Description

Analog Input,

VREF = 5 V

Digital Output

Code (Hex)

FSR − 1 LSB

+4.999962 V

0x7FFF1

Midscale + 1 LSB

+38.15 µV

0x0001

Midscale

0 V

0x0000

Midscale − 1 LSB

−38.15 µV

0xFFFF

−FSR + 1 LSB

−4.999962 V

0x8001

−FSR

−5 V

0x80002

This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).

This is also the code for an underranged analog input (VIN+ − VIN− below VGND).

COMP

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNVx

CONTROL

LOGIC

SWx+

LSB

SWx–

LSB

INx+

REFx

GND

INx–

MSB

16,384C

32,768C

16,384C

32,768C

100...000

100...001

100...010

011...101

011...110

011...111

ANALOG INPUT

+FSR – 1.5 LSB

+FSR – 1 LSB

–FSR + 1 LSB

–FSR

–FSR + 0.5 LSB

AD7690 Datasheet(PDF) 15 Page - Analog Devices

AD7690 Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL