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AD7690 Datasheet(PDF) 25 Page - Analog Devices

Part # AD7690
Description  Dual Differential 16-Bit, 1 MSPS PulSAR ADC 12.0 mW in QSOP
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7690 Datasheet(HTML) 25 Page - Analog Devices

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AD7903
Data Sheet
Rev. A | Page 24 of 28
APPLICATIONS INFORMATION
SIMULTANEOUS SAMPLING
By having two unique user interfaces, the AD7903 provides
maximum flexibility with respect to how conversion results are
accessed from the device. The AD7903 provides an option for
the two user interfaces to share the convert start (CNVx) signal
from the digital host, creating a 2-channel, simultaneous sampling
device. In applications such as control applications, where latency
between the sampling instant and the availability of results in
the digital host is critical, it is recommended that the AD7903
be configured as shown in Figure 51. This configuration allows
simultaneous data reads, in addition to simultaneous sampling.
However, this configuration also requires an additional data
input pin on the digital host. This scenario allows the fastest
throughput because it requires only 15 or 16 SCKx falling edges
(depending on the status of the busy indicator) to acquire data
from the ADC.
Alternatively, for applications where simultaneous sampling is
required but pins on the digital host are limited, the two user
interfaces on the AD7903 can be connected in one of the daisy-
chain configurations shown in Figure 47 and Figure 49. This daisy
chaining allows the user to implement simultaneous sampling
functionality while requiring only one digital host input pin.
This scenario requires 31 or 32 SCKx falling edges (depending
on the status of the busy indicator) to acquire data from the ADC.
Figure 51 shows an example of a simultaneous sampling system
using two data inputs for the digital host. The corresponding
timing diagram in Figure 52 shows a CS mode, 3-wire simul-
taneous sampling serial interface without a busy indicator.
However, any of the 3-wire or 4-wire serial interface timing
options can be used.
Figure 51. Potential Simultaneous Sampling Connection Diagram
Figure 52. Potential Simultaneous Sampling Serial Interface Timing
VIO1
VIO2
CONVERT
DATA IN 2
CLK
DIGITAL HOST
DATA IN 1
AD7903
ADC2
SDI2
SDO2
CNV2
SCK2
AD7903
ADC1
SDI1
SDO1
CNV1
SCK1
SDIx = 1
tCNVH
tCONV
tCYC
CNVx
ACQUISITION
ACQUISITION
tACQ
tSCK
tSCKL
CONVERSION
SCKx
tEN
tHSDO
1
2
3
14
15
16
tDSDO
tDIS
tSCKH
SDO1
D15
D14
D13
D1
D0
SDO2
D15
D14
D13
D1
D0



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