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Data Sheet

AD7903

Rev. A | Page 15 of 28

TYPICAL CONNECTION DIAGRAM

Figure 35 shows an example of the recommended connection

diagram for the AD7903 when multiple supplies are available.

ANALOG INPUTS

Figure 33 shows an equivalent circuit of the input structure of

the AD7903.

The two diodes, D1 and D2, provide ESD protection for the

analog inputs, INx+ and INx−. The analog input signal must never

exceed the reference input voltage (VREF) by more than 0.3 V. If

the analog input signal exceeds this level, the diodes become

forward biased and start conducting current. These diodes can

handle a forward-biased current of 130 mA maximum.

However, if the supplies of the input buffer (for example, the

supplies of the ADA4841-1 in Figure 35) are different from

those of the VREF, the analog input signal may eventually exceed

the supply rails by more than 0.3 V. In such a case (for example,

an input buffer with a short circuit), the current limitation can

be used to protect the device.

Figure 33. Equivalent Analog Input Circuit

The analog input structure allows for the sampling of the

differential signal between INx+ and INx−. By using these

differential inputs, signals common to both inputs, and within

the allowable common-mode input range, are rejected.

Figure 34. Analog Input CMRR vs. Frequency

During the acquisition phase, the impedance of the analog inputs

(INx+ or INx−) can be modeled as a parallel combination of the

CPIN capacitor and the network formed by the series connection

of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

400 Ω and is a lumped component composed of serial resistors

and the on resistance of the switches. CIN is typically 30 pF and

is mainly the ADC sampling capacitor.

During the sampling phase, where the switches are closed, the

input impedance is limited to CPIN. RIN and CIN make a one-pole,

low-pass filter that reduces undesirable aliasing effects and limits

noise.

When the source impedance of the driving circuit is low, the

AD7903 can be driven directly. Large source impedances

significantly affect the ac performance, especially THD. The

dc performances are less sensitive to the input impedance. The

maximum source impedance depends on the amount of THD

that can be tolerated. The THD degrades as a function of the

source impedance and the maximum input frequency.

Figure 35. Typical Application Diagram with Multiple Supplies

CPIN

REFx

RIN

CIN

INx+ OR INx–

GND

10k

100k

10M

FREQUENCY (Hz)

AD7903

ADCx

3-WIRE INTERFACE

2.5V

V+

1.8V TO 5V

100nF

10µF2

100nF

REFx

INx+

INx–

VDDx

VIOx SDIx

CNVx

SCKx

SDOx

GND

REF1

V+

V–

0V TO VREF

2.7nF

V+

V–

VREF TO 0V

ADA4841-1 3

2.7nF

1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.

2CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

SEE RECOMMENDED LAYOUT IN FIGURE 54.

3SEE THE DRIVER AMPLIFIER CHOICE SECTION.

4OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.

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