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Data Sheet

AD5696/AD5694

Rev. A | Page 17 of 24

SERIAL INTERFACE

The AD5696/AD5694 have a 2-wire, I2C-compatible serial

interface (see the I2

C-Bus Specification, Version 2.1, January

2000, available from Philips Semiconductor). See Figure 2 for a

timing diagram of a typical write sequence. The AD5696/AD5694

can be connected to an I2C bus as slave devices, under the control

of a master device. The AD5696/AD5694 support standard

(100 kHz) and fast (400 kHz) data transfer modes. Support is

not provided for 10-bit addressing or general call addressing.

Input Shift Register

The input shift register of the AD5696/AD5694 is 24 bits wide.

Data is loaded into the device, MSB first, as a 24-bit word under

the control of the serial clock input, SCL. The first eight MSBs

make up the command byte (see Figure 35 and Figure 36).

•

The first four bits of the command byte are the command

bits (C3, C2, C1, and C0), which control the mode of oper-

ation of the device (see Table 8).

•

The last four bits of the command byte are the address bits

(DAC D, DAC C, DAC B, and DAC A), which select the

DAC that is operated on by the command (see Table 9).

The 8-bit command byte is followed by two data bytes, which

contain the data-word. For the AD5696, the data-word comprises

the 16-bit input code (see Figure 35); for the AD5694, the data-

word comprises the 12-bit input code followed by four don’t care

bits (see Figure 36). The data bits are transferred to the input

shift register on the 24 falling edges of SCL.

Commands can be executed on one DAC channel, any two or

three DAC channels, or on all four DAC channels, depending

on the address bits selected (see Table 9).

Table 8. Command Definitions

Command Bits

Command

No operation

Write to Input Register n (dependent

on LDAC)

Update DAC Register n with contents

of Input Register n

Write to and update DAC Channel n

Power down/power up DAC

Hardware LDAC mask register

Software reset (power-on reset)

Reserved

X = don’t care.

Table 9. Address Bits and Selected DACs

Address Bits

Selected DAC Channels1

DAC D

DAC C

DAC B

DAC A

DAC B

DAC A and DAC B

DAC C

DAC A and DAC C

DAC B and DAC C

DAC A, DAC B, and DAC C

DAC D

DAC A and DAC D

…

All DACs

Any combination of DAC channels can be selected using the address bits.

Figure 35. Input Shift Register Contents, AD5696

Figure 36. Input Shift Register Contents, AD5694

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

D15

D14

D13

D12

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE