AD5686 datasheet(18/24 Pages) AD

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AD5696/AD5694

Data Sheet

Rev. A | Page 18 of 24

WRITE AND UPDATE COMMANDS

For more information about the LDAC function, see the Load

DAC (Hardware LDAC Pin) section.

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When LDAC is low, the

input register is transparent (if not controlled by the LDAC

mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected by the address bits

(see Table 9) and updates the DAC outputs directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly, independent of the state

of the LDAC pin.

I2C SLAVE ADDRESS

The AD5696/AD5694 have a 7-bit I2C slave address. The five

MSBs are 00011, and the two LSBs (A1 and A0) are set by the

state of the A1 and A0 address pins. The ability to make hard-

wired changes to A1 and A0 allows the user to incorporate up

to four AD5696/AD5694 devices on one bus (see Table 10).

Table 10. Device Address Selection

A1 Pin Connection

A0 Pin Connection

A1 Bit

A0 Bit

GND

VLOGIC

GND

VLOGIC

SERIAL OPERATION

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address.

2. The slave device with the transmitted address responds by

pulling SDA low during the 9th clock pulse (this is called

the acknowledge bit). At this stage, all other devices on the

bus remain idle while the selected device waits for data to

be written to, or read from, its input shift register.

3. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

Transitions on the SDA line must occur during the low period

of SCL; SDA must remain stable during the high period of SCL.

4. After all data bits are read or written, a stop condition is

established. In write mode, the master pulls the SDA line high

during the 10th clock pulse to establish a stop condition. In

read mode, the master issues a no acknowledge for the 9th

clock pulse (that is, the SDA line remains high). The master

then brings the SDA line low before the 10th clock pulse and

then high again during the 10th clock pulse to establish a

stop condition.

WRITE OPERATION

When writing to the AD5696/AD5694, the user must begin with

a start command followed by an address byte (R/W = 0), after

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. The AD5696/AD5694 require two bytes of

data for the DAC and a command byte that controls various DAC

functions. Three bytes of data must, therefore, be written to the

DAC with the command byte followed by the most significant

data byte and the least significant data byte, as shown in Figure 37.

All these data bytes are acknowledged by the AD5696/AD5694.

A stop condition follows.

Figure 37. I2C Write Operation

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

SCL

START BY

MASTER

ACK BY

AD5696/AD5694

ACK BY

AD5696/AD5694

SDA

R/W

DB23

DB22 DB21

DB20

DB19 DB18

DB17

DB16

ACK BY

AD5696/AD5694

ACK BY

AD5696/AD5694

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14

DB13 DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

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