AD5696/AD5694

Data Sheet

Rev. A | Page 20 of 24

POWER-DOWN OPERATION

Command 0100 is designated for the power-down function. The

AD5696/AD5694 provide three separate power-down modes

(see Table 11). These power-down modes are software program-

mable by setting Bit DB7 to Bit DB0 in the input shift register

(see Table 12). Two bits are associated with each DAC channel.

Table 11 shows how the state of these two bits corresponds to

the mode of operation of the device.

Table 11. Modes of Operation

Operating Mode

PDx1

PDx0

Normal Operation

0

0

Power-Down Modes

1 kΩ to GND

0

1

100 kΩ to GND

1

0

Three-State

1

1

Any or all DACs (DAC A to DAC D) can be powered down

to the selected mode by setting the corresponding bits in the

input shift register. See Table 12 for the contents of the input

shift register during the power-down/power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the DAC selected)

in the input shift register are set to 0, the parts work normally

with their normal power consumption of 0.59 mA at 5 V. When

Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1,

the part is in power-down mode. In power-down mode, the

supply current falls to 4 μA at 5 V.

In power-down mode, the output stage is internally switched

from the output of the amplifier to a resistor network of known

values. In this way, the output impedance of the part is known

when the part is in power-down mode.

Table 11 lists the three power-down options. The output is

connected internally to GND through either a 1 kΩ or a 100 kΩ

resistor, or it is left open-circuited (three-state). The output stage

is illustrated in Figure 39.

Figure 39. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when power-down

mode is activated. However, the contents of the DAC registers

are unaffected in power-down mode, and the DAC registers can

be updated while the device is in power-down mode. The time

LOAD DAC (HARDWARE LDAC PIN)

The AD5696/AD5694 DACs have double buffered interfaces

consisting of two banks of registers: input registers and DAC

registers. The user can write to any combination of the input

registers (see Table 9). Updates to the DAC registers are con-

trolled by the LDAC pin.

Figure 40. Simplified Diagram of Input Loading Circuitry for a Single DAC

Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1

DB23

(MSB)

DB22

DB21

DB20

DB19 to DB16

DB15

to DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

(LSB)

0

1

0

0

X

X

PDD1

PDD0

PDC1

PDC0

PDB1

PDB0

PDA1

PDA0

Command bits (C3 to C0)

Address bits

(don’t care)

Don’t

care

Power-down

select, DAC D

Power-down

select, DAC C

Power-down

select, DAC B

Power-down

select, DAC A

1

X = don’t care.

RESISTOR

NETWORK

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

SDA

SCL

DAC

REGISTER

INPUT SHIFT

REGISTER

OUTPUT

AMPLIFIER

LDAC

INPUT

REGISTER

12-/16-BIT

DAC