CS4225 datasheet(11/30 Pages) CIRRUS

11 / 30 page

46.5dB of gain in 1.5dB steps. The gain is ad-

justable only by software control. Level changes

only take effect on zero crossings to minimize

audible artifacts. If there is no zero crossing,

then the requested level change will occur after a

time-out of 511 frames (10.6ms at 48kHz frame

rate). There is a separate zero crossing detector

for each channel.

Analog Outputs

Line Level Outputs

AOUT1, AOUT2, AOUT3 and AOUT4 output a

1Vrms level for full scale, centered around

+2.1V. Figure 1 shows the recommended 1.0

µF

dc blocking capacitor with a 40k

Ω resistor to

ground. When driving impedances greater than

10k

Ω, this provides a high pass corner of 20Hz.

These outputs may be muted.

Output Level Attenuator

The DAC outputs are each routed through an at-

tenuator, which is adjustable in 1dB steps.

Output attenuation is available via software con-

trol only. Level changes are implemented such

that the noise is attenuated by the same amount

as the signal (equivalent to using an analog at-

tenuator after the signal source), until the

residual output noise is equal to the noise floor

in the mute state. Level changes only take effect

on zero crossings to minimize audible artifacts.

If there is no zero crossing, then the requested

level change will occur after a time-out of 511

frames (10.6ms at 48kHz frame rate). There is a

separate zero crossing detector for each channel.

Each output can be independently muted via

mute control bits. In addition, the CS4225 has an

optional mute on consecutive zeros feature,

where each DAC output will mute if it receives

512 consecutive zeros. A single non-zero value

will unmute the DAC output.

ADC and DAC Coding

The CS4225 converters use 2’s complement cod-

ing. Table 1 shows the ADC and DAC transfer

functions.

Calibration

Both output offset voltage and input offset error

are minimized by an internal calibration cycle.

At least one calibration cycle must be invoked

after power up. A calibration will occur any time

the part comes out of reset, including the power-

up reset. For the most accurate calibration, some

time must be allowed between powering up the

CS4225, or exiting the power-down state, and in-

itiating a calibration cycle, to allow the voltage

reference to settle. This is achieved by holding

RST/PDN low for at least 50ms after power up

or exiting power-down mode. Input offset error

will be calibrated for all inputs and outputs.

A calibration takes 192 frames to complete,

based on the frequency of the VCO of the inter-

16-bit ADC/DAC

12-bit ADC

Input/

2’s

Input

Output

Complement

Complement Voltage*

Voltage*

Code

+1.400000

7FFF

7FF

+1.40000

+1.399957

7FFE

7FE

+139864

+0.000064

0001

001

+0.00204

+0.000021

0000

000

+0.00068

-0.000021

FFFF

FFF

-0.00068

-0.000064

FFFE

FFE

-0.00204

-1.399957

8001

801

-1.39864

-1.400000

8000

800

-1.40000

*Nominal voltage relative to CMOUT (Typ 2.1V), no

gain or attenuation. Actual measured voltage will be

modified by the gain error and offset error specifica-

tions.

Table 1 - ADC/DAC Input and Output Coding Table

CS4225

DS86PP8

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