CS4225 datasheet(20/30 Pages) CIRRUS

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Hardware Mode

Hardware mode is selected by connecting the

H/S pin to VD. In hardware mode, only certain

functions are available:

- de-emphasis,

- digital interface formats 0, 1 and 2, and DSP

format 4,

- auxiliary audio port master/slave selection,

- CLKOUT and XTI frequencies are restricted,

- use of PLL is tied to master/slave selection,

- the PLL locks to LRCKAUX only,

- will mute on consecutive zeros.

In addition, the input gain is set to 0dB (no

gain), and the attenuator is set to 0dB (no attenu-

ation). The DAC mute bits are set to 0 (not

muted). The DSP port and Auxiliary port serial

clocks are set to 64 bits per Fs period.

In hardware mode, the DSP port is always in

slave mode. The IF1 pin selects the Auxiliary

port to be master or slave (low for master, high

for slave). When the Auxiliary port is a master,

XTI is the clock source and the PLL is off.

CKF0 and CKF1 pins define both XTI and

CLKOUT frequencies as follows:

When the Auxiliary port is a slave, LRCKAUX

is the clock source at 1 Fs, the PLL is enabled.

CKF1 and CKF0 determine CLKOUT as fol-

lows:

Functions only available in software mode in-

clude:

- input gain adjust & output level adjust,

- digital interface format 3, DSP format 5,

- more clocking flexibility,

- DAC muting,

- setting of number of bit clocks per Fs period,

- turn off mute upon consecutive zeros function,

- 12-bit ADC clipping indicator,

- PLL lock flag,

- routing the AINAUX signal to a 16-bit ADC,

- hold last sample on error.

Power Supply and Grounding

The CS4225, along with associated analog cir-

cuitry, should be positioned near to the edge of

your circuit board, and have its own, separate,

ground plane (see Figure 9). Preferably, it should

also have its own power plane. The +5V supply

must be connected to the CS4225 via a ferrite

bead, positioned closer than 1" to the device. A

single connection between the CS4225 ground

and the board ground should be positioned as

shown in Figure 9. Figure 10 shows the recom-

mended decoupling capacitor layout. Also see

Crystal’s layout Applications Note, and the

CDB4225 evaluation board data sheet for recom-

mended layout of the decoupling components.

The CS4225 will mute the analog outputs if the

supply drops below approximately 4 volts.

ADC and DAC Filter Response Plots

Figures 11 through 18 show the overall fre-

quency response, passband ripple and transition

band for the CS4225 ADC’s and DAC’s. Figure

17 shows the DAC’s deviation from linear phase.

The 12-bit ADC output is fully decimated to Fs,

but is not filtered. Figure 18 shows the noise

floor of the output, along with a low frequency

full scale signal. External digital filtering is nec-

essary to achieve the desired trade off between

measurement bandwidth and dynamic range.

CKF1

CKF0

XTI

CLKOUT

256 Fs

384 Fs

256 Fs

512 Fs

256 Fs

512 Fs

CKF1

CKF0

CLKOUT

256 Fs

384 Fs

512 Fs

1 Fs

CS4225

DS86PP8

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