CS4225 datasheet(14/30 Pages) CIRRUS

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Digital Interfaces

There are 3 digital interface ports: the audio DSP

port, the auxiliary digital audio port and the con-

trol port. In hardware mode (H/S pin high) the

control port is disabled, and various modes can

be set via pins. In hardware mode, control of the

input gain, output level and some modes are not

possible.

Audio DSP Serial Interface Signals

The serial interface clock, SCLK, is used for

transmitting and receiving audio data. SCLK can

be generated by the CS4225 (master mode) or it

can be input from an external SCLK source

(slave mode). The number of SCLK cycles in

one system sample period is programmable to be

32, 48, or 64. When SCLK is an input, 32

SCLK’s per system sample period is not recom-

mended, due to potential interference effects; 64

SCLK’s per sample period should be used in-

stead.

The Left/Right clock (LRCK) is used to indicate

left and right data, also the start of a new sample

period. It may be output from the CS4225, or it

may be generated from an external controller.

The frequency of LRCK is equal to the system

sample rate, Fs.

SDIN1 and SDIN2 are the data input pins, each

of which drives a pair of DACs. SDIN1 left data

is for DAC #1, SDIN1 right data is for DAC #2,

SDIN2 left data is for DAC #3, and SDIN2 right

data is for DAC #4. SDOUT1 carries the data

from the 2 16-bit ADCs. SDOUT2 carries the

data from the 12-bit ADC. The audio DSP port

may also be configured so that all 4 DAC’s data

is input on SDIN1, and all 3 ADC’s data is out-

put on SDOUT1.

Audio DSP Serial Interface Formats

The audio DSP port supports 5 alternate formats,

shown in Figures 3, 4, and 5. These formats are

chosen through the DSP Port Mode Byte in soft-

ware mode. In hardware mode, four formats are

available as selected by the DIF and IF0 pins.

The 12-bit ADC data format is similar to the 16-

bit data format. The 12-bit data is positioned to

the most significant end of a 16-bit field, with

the lower 4 bits set to zero. The resulting 16-bit

value is output on SDOUT2 in both the left and

right channel positions. The format will be the

same as the selected SDOUT1 format.

Figure 5 shows the timing for format 4, where

all 4 DAC data words are presented on SDIN1,

and the 3 ADC data words are presented on

SDOUT1.

Format 5 is a combination mode. The data out-

put is as in Format 1, on the SDOUT1 and

SDOUT2 pins. The data input is as in Format 4

on SDIN1. In both format 4 and 5, LRCK duty

cycle is 50% if it is an output.

MSB

LSB

MSB

LRCK

SCLK

SDIN1

LSB

MSB

LSB

MSB

LSB

MSB

DAC #1

DAC #2

DAC #3

DAC #4

MSB

LSB

MSB

SDOUT1

LSB

MSB

Left ADC

Right ADC

4 0's

AUX ADC

12-Bits

AUX ADC

12-Bits

Figure 5 - One data line mode (Format 4)

CS4225

DS86PP8

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