CS49400 datasheet(61/100 Pages) CIRRUS

61 / 100 page

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register (A1=0, A0=1).

Note that only the Host Control register can be

read using a byte read. The address must be

maintained for the duration of the read cycle,

and is latched on the falling edge of CS.

Host Control:

A[1:0]==01b.

2) The host initiates a read cycle by driving the CS

and RD pins low (bus must be tri-stated by this

time).

3) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the value of

the selected register from the HDAT[7:0] pins

of DSPC.

4) The host should now terminate the read cycle

by driving the CS and RD pins high.

6.3.5.4 Reading a 32-bit (4-byte) Word from

DSPC in Intel Mode

Information provided in this section is intended as

a functional description of how to read control

information from DSPC. The system designer must

ensure that all of the timing constraints of the Intel

Parallel Host Mode Read Cycle are met.

The flow diagram shown in Figure 45, "Intel

Mode, 32-Bit (4-Byte) Read Flow Diagram for

DSPC" on page 62 illustrates the sequence of

events that define a 4-byte read in Intel mode. 4-

byte (32-bit) reads should only be done with the

Host Message register. The protocol presented in

Figure 45 will now be described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register (A1=A0=0). Note

that only the Host Message register can be read

using a 4-byte read cycle. The address must be

maintained for the duration of the read cycle,

and is latched on the falling edge of CS.

Host Message:

A[1:0]==00b.

ADDRESSAPARALLELI/OREGISTER

(A[1:0] SETAPPROPRIATELY)

CS(HIGH)

CS(LOW)

WR(LOW)

WRITEMS_BYTETO

HDAT[7:0]

WR(HIGH)

WR(LOW)

WRITEBYTE_BTO

HDAT[7:0]

WR(HIGH)

WR(LOW)

WRITEBYTE_ATO

HDAT[7:0]

WR(HIGH)

WR(LOW)

WRITELS_BYTETO

HDAT[7:0]

WR(HIGH)

Figure 43. Intel Mode, 32-bit (4-byte) Write Flow

Diagram for DSPC

CS49400 Datasheet(PDF) 61 Page - Cirrus Logic

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