CS49400 datasheet(67/100 Pages) CIRRUS

67 / 100 page

DSPC.

11) The host indicates the byte has been read by

driving DS high.

12) The host latches out the next byte by driving

DS low.

13) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the least

significant byte (bits 7:0) of the selected

14) The host indicates the byte has been read by

driving DS high.

15) The host should now terminate the read cycle

by driving the CS pin high.

6.3.7 Procedures for Parallel Host Mode

Communication for DSPC

6.3.7.1 Control Write in a Parallel Host Mode

for DSPC

When writing control data to DSPC, the same

protocol is used whether the host is writing a

control message or an entire executable download

image. Messages sent to DSPC should be written

most significant byte first. Likewise, downloads of

the application code should also be performed most

significant byte first.

The example shown in this section can be

generalized to fit any control write situation. The

generic function ‘Read_Byte_*()’ is used in the

following example as a generalized reference to

either Read_Byte_MOT() (read a byte in Motorola

mode) or Read_Byte_INT() (read a byte in Intel

mode), and ‘Write_Byte_*()’ is a generic reference

to Write_Byte_MOT() (write a byte in Motorola

mode) or Write_Byte_INT() (write a byte in Intel

mode).

Similarly,

the

generic

function

‘Read_Word_*()’ is used in the following example

generalized

reference

either

Read_Word_MOT() (read a 32-bit word in

Motorola mode) or Read_Word_INT() (read a 32-

bit word in Intel mode), and ‘Write_Word_*()’ is a

generic reference to Write_Word_MOT() (write a

32-bit

word

Motorola

mode)

Write_Word_INT() (write a 32-bit word in Intel

mode). Figure 50 shows a typical write sequence.

The protocol presented in Figure 50 will now be

described in detail.

1) When the host is communicating with DSPC,

the host must verify that DSPC is ready to

accept a new 32-bit control word. If DSPC has

not read the previous word from the control

port, it will be unable to receive another word.

2) In order to determine whether DSPC is ready to

accept a new 32-bit control word the host must

read the HINBSY bit of the Host Control

selected

communication

mode

(Intel

Motorola). If HINBSY is high, then the DSP is

not prepared to accept a new control word, and

the host should poll the Host Control Register

again. If HINBSY is low, then the host may

write a control word (32-bits) into the Host

MORE BYTES

TO WRITE?

READ_BYTE_*(HOST

CONTROL REGISTER)

FINISHED

WRITE_WORD_*(HOST

MESSAGE REGISTER)

HINBSY == 1

Figure 50. Typical Parallel Host Mode Control

Write Sequence Flow Diagram for DSPC

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