CS49400 datasheet(44/100 Pages) CIRRUS

44 / 100 page

1) An SPI read transaction is initiated by DSPAB

dropping FINTREQ, signaling that it has data

to be read.

2) The host responds by driving chip select (FCS)

low.

3) This is followed by a 7-bit address and the

read/write bit set high for a read. The address

for DSPAB defaults to 1000000b. It is

necessary to clock this address in prior to any

transfer in order for DSPAB to acknowledge

the read. In other words a byte of 0x81 should

be clocked into the device preceding any read.

The 0x81 byte represents the 7-bit address

1000000b, and the least significant bit set to 1

to designate a read.

4) After the falling edge of the serial control clock

(FSCCLK) for the read/write bit, the data is

ready to be clocked out on the control data out

pin (FCDOUT). Data clocked out by the host is

valid on the rising edge of FSCCLK. Data

transitions occur on the falling edge of

FSCCLK. The serial clock should be default

low so that eight transitions from low to high to

low will occur for each byte.

5) If FINTREQ is still low, another byte should be

clocked out of DSPAB. Please see the

discussion below for a complete description of

FINTREQ behavior.

6) When FINTREQ is released, the chip select

line of DSPAB should be taken high to end the

read transaction.

Understanding the role of FINTREQ is important

for

successful

communication. FINTREQ

guaranteed to remain low (once it has gone low)

until the second to last rising edge of FSCCLK of

the last byte to be transferred out of DSPAB. If

thereis nomoredatatobetransferred, FINTREQ

will go high at this point. For SPI this is the rising

edge for the second to last bit of the last byte to be

transferred. After going high, FINTREQ is

guaranteed to stay high until the next rising edge of

FSCCLK. This end of transfer condition signals the

host to end the read transaction by clocking the last

data bit out and raising FCS. If FINTREQ is still

low after the second to last rising edge of FSCCLK,

the host should continue reading data from the

serial control port.

It should be noted that all data should be read out of

the serial control port during one transaction or a

loss of data will occur. In other words, all data

should be read out of the chip until FINTREQ

signals the last byte by going high as described

above. Please see Section 6.1.3

“FINTREQ

Behavior: A Special Case” on page 48 for a more

detailed description of FINTREQ behavior.

FINTREQ

(LOW )?

FINTRE Q STILL

LO W ?

FCS HIGH

FCS LOW

READ DA TA BYTE

W RITE ADD RES S BYTE

W ITH MODE BIT SET TO

1 FOR READ

Figure 32. SPI Read Flow Diagram for DSPAB

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