CS49400 datasheet(62/100 Pages) CIRRUS

62 / 100 page

2) The host initiates a read cycle by driving the CS

and RD pins low (bus must be tri-stated by this

time).

3) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the most

significant data byte (bits 31:24) from the

HDAT[7:0] pins of DSPC.

4) The host drives RD high to indicate that the

data byte has been read.

5) The host drives RD low to clock out the next

data byte.

6) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read BYTE_B (bits

23:16) from the HDAT[7:0] pins of DSPC.

7) The host drives RD high to indicate that the

data byte has been read.

8) The host drives RD low to clock out the next

data byte.

9) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read BYTE_A

(bits 15:8) from the HDAT[7:0] pins of DSPC.

10) The host drives RD high to indicate that the

data byte has been read.

11) The host drives RD low to clock out the next

data byte.

12) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the least

significant data byte (bits 7:0) from the

HDAT[7:0] pins of DSPC.

13) The host drives RD high to indicate that the

data byte has been read.

14) The host should now terminate the read cycle

by driving the CS pin high.

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

CS (HIGH)

CS (LOW)

RD (LOW)

READ MS_BYTE FROM

HDAT[7:0]

RD (HIGH)

RD (LOW)

READ BYTE_B FROM

HDAT[7:0]

RD (HIGH)

RD (LOW)

READ BYTE_A FROM

HDAT[7:0]

RD (HIGH)

READ LS_BYTE FROM

HDAT[7:0]

RD (HIGH)

RD (LOW)

Figure 45. Intel Mode, 32-Bit (4-Byte) Read Flow

Diagram for DSPC

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