DS18B20

19 of 27

NOTES:

1. Temperature conversion takes up to 750 ms. After receiving the Convert T protocol, if the part does

may take place on the 1-Wire bus for at least this period after a Convert T command has been issued.

DQ line for the DS18B20 must be held high for at least 10 ms to provide power during the copy

process. As such, no other activity may take place on the 1-Wire bus for at least this period after a

Copy Scratchpad command has been issued.

3. All 3 bytes must be written before a reset is issued.

READ/WRITE TIME SLOTS

DS18B20 data is read and written through the use of time slots to manipulate bits and a command word to

specify the transaction.

Write Time Slots

A write time slot is initiated when the host pulls the data line from a high logic level to a low logic level.

There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots

must be a minimum of 60

µs in duration with a minimum of a 1-µs recovery time between individual

write cycles.

The DS18B20 samples the DQ line in a window of 15

µs to 60 µs after the DQ line falls. If the line is

high, a Write 1 occurs. If the line is low, a Write 0 occurs (see Figure 12).

For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then

released, allowing the data line to pull up to a high level within 15

µs after the start of the write time slot.

For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain

low for 60

µs.

Read Time Slots

The host generates read time slots when data is to be read from the DS18B20. A read time slot is initiated

when the host pulls the data line from a logic high level to logic low level. The data line must remain at a

low logic level for a minimum of 1

µs; output data from the DS18B20 is valid for 15 µs after the falling

edge of the read time slot. The host therefore must stop driving the DQ pin low in order to read its state

15

µs from the start of the read slot (see Figure 12). By the end of the read time slot, the DQ pin will pull

back high via the external pullup resistor. All read time slots must be a minimum of 60

µs in duration

with a minimum of a 1-

µs recovery time between individual read slots.

µs. Figure 14 shows that

master sample time towards the end of the 15-

µs period.