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DS1994 Datasheet(PDF) 22 Page - Dallas Semiconductor |
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DS1994 Datasheet(HTML) 22 Page - Dallas Semiconductor |
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22 / 22 page ![]() DS1994 22 of 22 Reset Time Low (Note 7) tRSTL 480 960 ms Presence Detect High tPDH 15 60 ms Presence Detect Low tPDL 60 240 ms Note 1: All voltages are referenced to ground. Note 2: VPUP = external pullup voltage. Note 3: Input load is to ground. Note 4: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 5: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 ms of this falling edge and remains valid for 14ms minimum. (15ms total from falling edge on 1-Wire bus.) Note 6: Capacitance on the data line could be 800pF when power is first applied. If a 5k W resistor is used to pull up the data line to VPUP, 5 ms after power has been applied, the parasite capacitance does not affect normal communications. Note 7: The reset low time (tRSTL) should be restricted to a maximum of 960 ms to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses. Note 8: Guaranteed by design, not production tested. |
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