DS1994

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Figure 1. DS1994 BLOCK DIAGRAM

SRAM

TIMEKEEPING

HOLDING REGISTERS

FUNCTIONS

16 PAGES of

256-BITs

& COUNTERS

INTERNAL REGISTERS

32.768 kHz

OSCILLATOR

256-BIT

SCRATCHPAD

1-W

ROM

CONTROL

FUNCTION

64-BIT

ROM

LASERED

PARASITE-

CIRCUITRY

POWERED

MEMORY

FUNCTION

CONTROL

1-WIRE

PORT

3V LITHIUM

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever

the data input is high. The data line provides sufficient power as long as the specified timing and voltage

requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,

lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM can still be read

normally.

64-BIT LASERED ROM

Each DS1994 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.

The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.)

The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates,

Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits

are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is

shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After

the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in

the 8 bits of CRC should return the shift register to all zeros.

Figure 2. 64-BIT LASERED ROM

MSB

LSB

8-Bit CRC Code

48-Bit Serial Number

8-Bit Family Code (04h)

MSB

LSB MSB

LSB MSB

LSB