MA17501 datasheet(10/35 Pages) DYNEX

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MA17501

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3.6.4 Privileged Instruction Fault (PIFN)

lnput. PlFN low is an indication to the Execution Unit that a

fault, requiring the current MlL-STD-1750A instruction to be

aborted, has occurred. The faults that cause the instruction

abort are 0, 5, and 8 which are, respectively, memory protect

error ((IU)MPROEN low), an out-of-bounds memory/input-

output address ((lU)EXADE low), or a bus fault timeout. ln

response to PIFN low, the EU maintains AS low, DSN high,

and forces the M/lON signal high for two machine cycles. ln

addition, the EU will internally complete the current SYNCN

cycle and resume operation. This allows the Control Unit to

sequence to the interrupt handling routine without affecting the

bus status.

3.6.5 Branch or Jump Control (T1)

Output. The Execution Unit raises the T1 signal high to

indicate a microcode conditional branch condition is true. The

Control Unit accepts T1 and feeds it into the microcode

address multiplexer where microinstruction branches are

effected.

3.6.6 Test Microword (TESTN)

lnput. The TESTN signal is used during chip test to load 40-

bit microinstructions into the EU execution register. TESTN

low loads E39 (MSB) to E20, and TESTN high loads E19 to

E00 (LSB). TESTN should be pulled-up to VDD in customer

applications.

4.0 OPERATING MODES

The following discussions detail the MAS281 chip set

operating modes from the perspective of the Execution Unit.

MAS281 operating modes involving the MA17501 include: (1)

Initialisation, (2) lnstruction Execution, (3) Interrupt Servicing,

(4) Fault Servicing, (5) DMA Support, and (6) Software

Development Support.

4.1 INITIALISATION

RESET starts the chip set microcoded initialisation

sequence, but also affects the Execution Unit Circuitry directly.

When RESET is raised high, the Hold state acknowledge

signal (HLDAKN) is forced high thus releasing the MAS281

from the Hold state (if changing HOLDN is unable to release

the Hold state). RESET also forces the clock generation

circuitry to create a five OSC period machine cycle by

disabling state machine inputs that vary the machine cycle

length.

Upon releasing RESET, the EU Hold State circuitry is

enabled and the clock generation circuitry is allowed to

function normally. HOLDN will not have an effect on chip set

operation until the initialisation routine has completed because

the microcode branch to the Hold routine is disabled.

The microcoded initialisation routine clears the lnstruction

Counter (lC), Status Word Register (SW), and Register File

(R00-R15) and performs the BlT. The successful completion of

the BlT is necessary to guarantee the register file is cleared at

the end of the initialisation routine.

The microcoded BIT exercises all legal microinstruction bit

combinations and tests all internally accessible structures of

the MAS281. For the Execution Unit this includes the full

logic. Table 2 details the tests performed by each of the five

BlT subroutines.

lf any part of BlT fails, an error code identifying the failed

subroutine is loaded into the lnterrupt Unit Fault Register (via

the AD Bus), BlT is aborted, and NPU is left in the low state.

Table 2 defines the coding of the BlT results. (lNTREN enables

microcode control of the lnterrupt Unit (lU) to raise NPU high (if

BlT passes) and load BIT error codes (if BIT fails) into the lU

Fault Register).

The last action performed by the initialisation routine is to

load the instruction pipeline. Instruction fetches start at

memory location zero (page zero) from the Start-Up ROM (if

implemented). Whether or not BIT passes, the processor will

begin instruction execution at this point.

[NOTE: To complete initialisation and pass BIT, interrupt

and fault inputs must be high for the duration of the

initialisation routine. Also, the Timers A and B must be clocked

for BlT success.]

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