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Table 5: Absolute Maximum Ratings

6.0 ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Units

Supply Voltage

-0.5

7

V

Input Voltage

-0.3

V

Current Through Any Pin

-20

+20

mA

Operating Temperature

-55

125

°C

Storage Temperature

-65

150

°C

Note: Stresses above those listed may cause permanent

damage to the device. This is a stress rating only and

functional operation of the device at these conditions, or at

any other condition above those indicated in the operations

section of this specification, is not implied. Exposure to

absolute maximum rating conditions for extended periods

may affect device reliability.

Total Dose Radiation Not

Exceeding 3x10

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Supply Voltage

4.5

5.0

5.5

V

CMOS Input High Voltage (Note 1)

-

-

-

V

CMOS Input Low Voltage (Note 1)

-

-

-

V

TTL Input High Voltage (Note 2)

-

2.0

-

-

V

TTL Input Low Voltage (Note 2)

-

-

-

0.8

V

OSC Input High Voltage (Note 6)

-

4.0

-

-

V

OSC Input Low Voltage (Note 6)

-

-

-

1.0

V

CMOS Output High Voltage (Note 1)

4.0

-

-

V

CMOS Output Low Voltage (Note 1)

-

-

0.5

V

TTL Output High Voltage (Note 2)

3.5

-

-

V

TTL Output Low Voltage (Note 2)

-

-

0.4

V

Clock Output High Voltage (Note 3)

4.0

-

-

V

Clock Output Low Voltage (Note 3)

-

-

0.5

V

Input Leakage Current (Note 4)

-

-

±10

µA

Output Leakage Current (Note 4)

-

-

±50

µA

TESTN Input Pullup Current (Note 5)

-

-150

-300

µA

Operating Supply Current

-

25

35

mA

Static Supply Current

-

5

10

mA

Mil-Std-883, Method 5005, Subgroup 1, 2, 3.

Notes: 1. The following signals are CMOS compatible:

a) CMOS inputs: Microcode Bus, (M00-M19), TESTN, IRDYN and PIFN.

b) CMOS outputs: T1, OVIN, INTREN, SYSCLK1N, CLKPCN and CLK02N.

2. The following signals are TTL compatible:

a) TTL inputs: HOLDN, RESET, PAUSEN, RDYN and OSC.

b) TTL outputs: HOLDAKN and SYNCN.

c) TTL 3 state outputs: AS, DSN, M/ION, RD/WN and IN/OPN.

d) TTL 3 state I/O signals: Address/Data Bus (AD00-AD15).

3. The clock output pins, SYSCLK1N, SYNCLK, CLKPCN and CLK02N have a higher drive capability than the

standard outputs.

5. The TESTN input signal is used during chip test and has an integral pullup reistor. In normal operation TESTN is at

6. Guaranteed but not tested.

7.0 DC ELECTRICAL CHARACTERISTICS

Table 6: Operating DC Electrical Characteristics