ADP3650

Rev. A | Page 6 of 12

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OD

1

IN

2

BST

3

VCC

4

DRVH

8

SW

7

PGND

6

DRVL

5

ADP3650

TOP VIEW

(Not to Scale)

Figure 4. 8-Lead SOIC_N Pin Configuration

PIN 1

INDICATOR

1

2

3

4

7

8

6

5

TOP VIEW

(Not to Scale)

OD

BST

VCC

DRVH

NOTES

1. IT IS RECOMMENDED THAT THE

EXPOSED PAD AND THE PGND PIN

BE CONNECTED ON THE PCB.

SW

PGND

DRVL

ADP3650

IN

Figure 5. 8-Lead LFCSP_VD Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET while it is switching.

2

IN

Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. This pin should be closely connected to the source of the lower MOSFET. This pin is not internally

connected to the exposed pad on the LFCSP. It is recommended that this pin and the exposed pad be

connected on the PCB.

7

SW

Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source.

It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to

prevent the lower MOSFET from turning on until the voltage is below ~1 V.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

EP

Exposed pad

For the LFCSP, the exposed pad and the PGND pin should be connected on the PCB. For more information

about exposed pad packages, see the AN-772 Application Note at www.analog.com.