SL28EB742 datasheet(34/40 Pages) ETC2

34 / 40 page

SL28EB742

Preliminary Rev. 0.1

Table 12. 56-QFN Pin Definitions

Pin #

Name

Type

Description

PCIF/ITP_EN

I/O,

SE, PD

33 MHz free running clock output/3.3 V LVTTL input to enable SRC6

or CPU2_ITP (sampled on the CKPWRGD assertion).

0 = SRC6, 1 = CPU2

2CLKREQ3

I, PD

Active low input pin enables SRC3 (internal 100 k

 pull-down).

12_48M / SEL12_48

I/O, SE

12/48 MHz Clock output/3.3 V-tolerance input for 12 MHz or 48 MHz

selection (Sampled at CKPWRGD assertion) (internal 100 k

 pull-up).

0=48M, 1=12M

VDD_48

PWR

3.3 V Power supply

48M/FSA

I/O

Fixed 48 MHz clock output/3.3 V-tolerant input for CPU frequency

selection (internal 100 k

 pull-down).

GND_48

GND

Ground.

GND_48

GND

Ground.

DOT96

O, DIF Fixed true 96 MHz clock output.

9DOT96

O, DIF Fixed complement 96 MHz clock output.

FSB

I, PD

3.3 V-tolerant input for CPU frequency selection (internal 100 k

 pull-

down).

GND_SATA

GND

Ground.

SATA/SRC0

O, DIF 100 MHz True differential serial reference clock.

SATA/SRC0

O, DIF 100 MHz Complement differential serial reference clock.

VDD_SATA

PWR

3.3 V Power supply.

SRC1

O, DIF 100 MHz True differential serial reference clock.

SRC1

O, DIF 100 MHz Complement differential serial reference clock.

SRC2

O, DIF 100 MHz True differential serial reference clock.

SRC2

O, DIF 100 MHz Complement differential serial reference clock.

SRC3

O, DIF 100 MHz True differential serial reference clock.

SRC3

O, DIF 100 MHz Complement differential serial reference clock.

GND_SRC

GND

Ground.

VDD_SRC

PWR

3.3 V Power supply.

SRC4

O, DIF 100 MHz Complement differential serial reference clock.

SRC4

O, DIF 100 MHz True differential serial reference clock.

SRC5

O, DIF 100 MHz Complement differential serial reference clock.

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