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SL28EB742 Datasheet(PDF) 35 Page - List of Unclassifed Manufacturers |
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SL28EB742 Datasheet(HTML) 35 Page - List of Unclassifed Manufacturers |
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35 / 40 page ![]() SL28EB742 Preliminary Rev. 0.1 35 26 SRC5 O, DIF 100 MHz True differential serial reference clock. 27 GND_SRC GND Ground. 28 VDD_SRC PWR 3.3 V Power supply. 29 SRC6/CPU2_ITP O, DIF Selectable complementary differential CPU or SRC clock output. ITP_EN = 0 @ CKPWRGD assertion = SRC6 ITP_EN = 1 @ CKPWRGD assertion = CPU2 30 SRC6/CPU2_ITP O, DIF Selectable True differential CPU or SRC clock output. ITP_EN = 0 @ CKPWRGD assertion = SRC6 ITP_EN = 1 @ CKPWRGD assertion = CPU2 31 CPU1 O, DIF Complement differential CPU clock output. 32 CPU1 O, DIF True differential CPU clock output. 33 VDD_CPU PWR 3.3 V Power supply. 34 CPU0 O, DIF Complement differential CPU clock output. 35 CPU0 O, DIF True differential CPU clock output. 36 GND_CPU GND Ground. 37 SCLK I I2C compatible SCLOCK. 38 SDATA I/O I2C compatible SDATA. 39 CPU_STP I, PU 3.3 V-tolerant input for stopping CPU outputs (internal 100 k pull-up). 40 PCI/SRC_STP I, PU 3.3 V-tolerant input for stopping PCI and SRC outputs (internal 100 k pull-up). 41 XOUT O 14.318 MHz Crystal output, Float XOUT if using only CLKIN (Clock input). 42 XIN/CLKIN I 14.318 MHz Crystal input or 3.3 V, 14.318 MHz Clock Input 43 GND_REF GND Ground for REF clock. 44 GND_REF GND Ground for REF clock. 45 REF O 14.318 MHz reference output clock. 46 VDD_REF PWR 3.3 V Power Supply for REF clock. 47 VDD_REF PWR 3.3 V Power Supply for REF clock. 48 CKPWRGD/PD I 3.3 V LVTTL input. This pin is a level sensitive strobe used to deter- mine when latch inputs are valid and are ready to be sampled. After latch inputs are latched, this pin becomes a real-time active low input for asserting power down (PD); asynchronous active low input pin that stops all outputs except free running. Table 12. 56-QFN Pin Definitions (Continued) Pin # Name Type Description |
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