FG896 datasheet(63/166 Pages) MICROSEMI

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ProASIC3E Flash Family FPGAs

Revision 14

2-49

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by the Designer software when the user

instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-22. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-22 • LVDS Circuit Diagram and Board-Level Implementation

140



100



Z0 = 50 

165



165

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–

INBUF_LVDS

OUTBUF_LVDS

FPGA

Bourns Part Number: CAT16-LV4F12

FG896 Datasheet(PDF) 63 Page - Microsemi Corporation