FG896 datasheet(97/166 Pages) MICROSEMI

97 / 166 page

ProASIC3E Flash Family FPGAs

Revision 14

2-83

Embedded FlashROM Characteristics

Timing Characteristics

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-12 for more details.

Timing Characteristics

Figure 2-54 • Timing Diagram

tSU

tHOLD

tSU

tHOLD

tSU

tHOLD

tCKQ2

CLK

Address

Data

Table 2-102 • Embedded FlashROM Access Time

Parameter

Description

–2

–1

Std.

Units

tSU

Address Setup Time

0.53

0.61

0.71

tHOLD

Address Hold Time

0.00

tCK2Q

Clock to Out

16.23

18.48

21.73

FMAX

Maximum Clock Frequency

MHz

Table 2-103 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

–2

–1

Std.

Units

tDISU

Test Data Input Setup Time

0.50

0.57

0.67

tDIHD

Test Data Input Hold Time

1.00

1.13

1.33

tTMSSU

Test Mode Select Setup Time

0.50

0.57

0.67

tTMDHD

Test Mode Select Hold Time

1.00

1.13

1.33

tTCK2Q

Clock to Q (data out)

6.00

6.80

8.00

tRSTB2Q

Reset to Q (data out)

20.00 22.67

26.67

FTCKMAX

TCK Maximum Frequency

25.00 22.00

19.00

MHz

tTRSTREM

ResetB Removal Time

0.00

tTRSTREC

ResetB Recovery Time

0.20

0.23

0.27

tTRSTMPW

ResetB Minimum Pulse

TBD

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

FG896 Datasheet(PDF) 97 Page - Microsemi Corporation

FG896 Datasheet(HTML) 97 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL