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FG896 Datasheet(PDF) 71 Page - Microsemi Corporation |
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FG896 Datasheet(HTML) 71 Page - Microsemi Corporation |
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71 / 166 page  ProASIC3E Flash Family FPGAs Revision 14 2-57 Input Register Timing Characteristics Figure 2-27 • Input Register Timing Diagram 50% Preset Clear Out_1 CLK Data Enable t ISUE 50% 50% t ISUD t IHD 50% 50% t ICLKQ 1 0 t IHE t IRECPRE t IREMPRE t IRECCLR t IREMCLR t IWCLR t IWPRE t IPRE2Q t ICLR2Q t ICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-86 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 ns tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.41 0.48 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. |
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