ADC12H034 datasheet(39/53 Pages) TI1

39 / 53 page

ADC12030, ADC12032, ADC12034

ADC12038, ADC12H030, ADC12H032

ADC12H034, ADC12H038

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SNAS080K – JULY 1999 – REVISED MARCH 2013

for (8-bit) resolution the Output Code =

(2)

Round off to the nearest integer value between

−4096 to 4095 for 12-bit resolution and between −256 to 255 for

8-bit resolution if the result of the above equation is not a whole number.

Examples are shown in the table below:

VREF

−

VIN

−

Digital Output Code

+2.5V

+1V

+1.5V

0,1111,1111,1111

+4.096V

+3V

0,1011,1011,1000

+4.096V

+2.499V

+2.500V

1,1111,1111,1111

+4.096V

1,0000,0000,0000

5.0 INPUT CURRENT

At the start of the acquisition window (tA) a charging current flows into or out of the analog input pins (A/DIN1 and

A/DIN2) depending upon the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1

is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend upon the

actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With

MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically

1.6 k

Ω. The A/DIN1 and A/DIN2 mux on resistance is typically 750Ω.

6.0 INPUT SOURCE RESISTANCE

For low impedance voltage sources (<600

Ω), the input charging current will decay before the end of the S/H's

acquisition time of 2 µs (10 CCLK periods with fC = 5 MHz), to a value that will not introduce any conversion

errors. For high source impedances, the S/H's acquisition time can be increased to 18 or 34 CCLK periods. For

less ADC resolution and/or slower CCLK frequencies the S/H's acquisition time may be decreased to 6 CCLK

periods. To determine the number of clock periods (Nc) required for the acquisition time with a specific source

impedance for the various resolutions the following equations can be used:

12 Bit + Sign

NC = [RS + 2.3] × fC × 0.824

8 Bit + Sign

NC = [RS + 2.3] × fC × 0.57

where

•

fC is the conversion clock (CCLK) frequency in MHz

•

RS is the external source resistance in kΩ

(3)

As an example, operating with a resolution of 12 Bits+sign, a 5 MHz clock frequency and maximum acquisition

time of 34 conversion clock periods the ADC's analog inputs can handle a source impedance as high as 6 k

Ω.

The acquisition time may also be extended to compensate for the settling or response time of external circuitry

connected between the MUXOUT and A/DIN pins.

An acquisition starts at a falling edge of SCLK and ends at a rising edge of CCLK (see timing diagrams). If SCLK

and CCLK are asynchronous, one extra CCLK clock period may be inserted into the programmed acquisition

time for synchronization. Therefore, with asynchronous SCLK and CCLKs the acquisition time will change from

conversion to conversion.

7.0 INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, CH0–CH7, and analog

ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not

degrade the conversion accuracy.

8.0 NOISE

The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize

input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce

the effects of the noise sources.

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Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034

ADC12H038

ADC12H034 Datasheet(PDF) 39 Page - Texas Instruments

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