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AS5147 Datasheet(PDF) 11 Page - ams AG |
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AS5147 Datasheet(HTML) 11 Page - ams AG |
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11 / 35 page ![]() ams Datasheet: 2014-Jun-27 [v1-04] AS5147 – 11 Detaile d Desc rip t ion Figure 13: SPI Timing SPI Transaction An SPI transaction consists of a 16-bit command frame followed by a 16-bit data frame. Figure 14 shows the structure of the command frame. Figure 14: SPI Command Frame Parameter Description Min Max Units tL Time between CSn falling edge and CLK rising edge 350 ns tclk Serial clock period 100 ns tclkL Low period of serial clock 50 ns tclkH High period of serial clock 50 ns tH Time between last falling edge of CLK and rising edge of CSn tclk/2 ns tCSn High time of CSn between two transmissions 350 ns tMOSI Data input valid to falling clock edge 20 ns tMISO CLK edge to data output valid 20 ns tOZ Release bus time after CS rising edge. 10 ns Bit Name Description 15 PARC Parity bit (even) calculated on the command frame 14 R/W 0: Write 1: Read 13:0 ADDR Address to read or write |
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