WM1824

Production Data

w

PD, Rev 4.1, December 2011

10

POWER ON RESET CIRCUIT

Figure 3 Internal Power on Reset Circuit Schematic

The WM1824 includes an internal Power-On-Reset circuit, as shown in Figure 3, which is

used to reset the DAC digital logic into a default state after power up. The POR circuit is

powered by AVDD and has as its inputs VMID and LINEVDD. It asserts POR low if VMID or

LINEVDD are below a minimum threshold.

Figure 4 Typical Power Timing Requirements

Figure 4 shows a typical power-up sequence where LINEVDD comes up with AVDD. When

guarantee POR is asserted low and the chip is held in reset. In this condition, all writes to the

released high and access to the control interface and audio interface may take place. This

assumes that DBVDD is at a level within the recommended operating conditions.