Production Data

WM1824

w

PD, Rev 4.1, December 2011

13

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a

LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on

word length, BCLK frequency and sample rate, there may be unused BCLK cycles before

each LRCLK transition.

Figure 6 Left Justified Audio Interface (assuming n-bit word length)

In I

transition. The other bits up to the LSB are then transmitted in order. Depending on word

length, BCLK frequency and sample rate, there may be unused BCLK cycles between the

LSB of one sample and the MSB of the next.

Figure 7 I

DIGITAL AUDIO DATA SAMPLING RATES

The external master clock is applied directly to the MCLK input pin. In a system where there

are a number of possible sources for the reference clock, it is recommended that the clock

source with the lowest jitter be used for the master clock to optimise the performance of the

WM1824.

The WM1824 has a detection circuit that automatically determines the relationship between

the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system

clock periods. The MCLK must be synchronised with the LRCLK, although the device is

tolerant of phase variations or jitter on the MCLK.

If during sample rate change the ratio between MCLK and LRCLK varies more than once

within 1026 LRCLK periods, then it is recommended that the device be taken into the standby

state or the off state before the sample rate change and held in standby until the sample rate

change is complete. This will ensure correct operation of the detection circuit on the return to

the enabled state. For details on the standby state, please refer to the Power up and down

control section of the datasheet on page 15.