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WM1811A Datasheet(PDF) 272 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 272 Page - Wolfson Microelectronics plc |
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272 / 328 page  WM1811A Production Data w PD, November 2013, Rev 4.1 272 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 AIF2TXR_ENA 1 Enable AIF2DAC (Right) input path 0 = Disabled 1 = Enabled This bit must be set for AIF2 output of the AIF2ADC (Left) signal. For AIF3 output only, this bit can be set to 0. Register 0318h AIF2TX Control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R800 (0320h) AIF3 Control (1) 7 AIF3_LRCLK_INV 0 Right, left and I2S modes – LRCLK3 polarity 0 = normal LRCLK3 polarity 1 = invert LRCLK3 polarity DSP Mode – mode A/B select 0 = MSB is available on 2nd BCLK3 rising edge after LRCLK3 rising edge (mode A) 1 = MSB is available on 1st BCLK3 rising edge after LRCLK3 rising edge (mode B) 6:5 AIF3_WL [1:0] 10 AIF3 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Note - 8-bit modes can be selected using the “Companding” control bits. Note that this controls the AIF3 Mono PCM interface path only; it does not affect AIF3 inputs/outputs routed to AIF1 or AIF2. Register 0320h AIF3 Control (1) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R801 (0321h) AIF3 Control (2) 11:10 AIF3DAC_BOOS T [1:0] 00 AIF3 Input Path Boost 00 = 0dB 01 = +6dB (input must not exceed -6dBFS) 10 = +12dB (input must not exceed -12dBFS) 11 = +18dB (input must not exceed -18dBFS) Note that this controls the AIF3 Mono PCM interface path only; it does not affect DACDAT3 input to AIF1 or AIF2. 4 AIF3DAC_COMP 0 AIF3 Receive Companding Enable 0 = Disabled 1 = Enabled Note that this controls the AIF3 Mono PCM interface path only; it does not affect DACDAT3 input to AIF1 or AIF2. 3 AIF3DAC_COMP MODE 0 AIF3 Receive Companding Type 0 = µ-law 1 = A-law Note that this controls the AIF3 Mono PCM interface path only; it does not affect DACDAT3 input to AIF1 or AIF2. |
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