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WM1811A Datasheet(PDF) 273 Page - Wolfson Microelectronics plc |
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WM1811A Datasheet(HTML) 273 Page - Wolfson Microelectronics plc |
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273 / 328 page ![]() Production Data WM1811A w PD, November 2013, Rev 4.1 273 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 AIF3ADC_COMP 0 AIF3 Transmit Companding Enable 0 = Disabled 1 = Enabled Note that this controls the AIF3 Mono PCM interface path only; it does not affect ADCDAT3 output from AIF1 or AIF2. 1 AIF3ADC_COMP MODE 0 AIF3 Transmit Companding Type 0 = µ-law 1 = A-law Note that this controls the AIF3 Mono PCM interface path only; it does not affect ADCDAT3 output from AIF1 or AIF2. 0 AIF3_LOOPBACK 0 AIF3 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (AIF3 Mono PCM data output is directly input to AIF3 Mono PCM data input). Register 0321h AIF3 Control (2) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R802 (0322h) AIF3DAC Data 0 AIF3DAC_DAT_I NV 0 AIF3 Receive Data Invert 0 = Not inverted 1 = Inverted Note that this controls the AIF3 Mono PCM interface path only; it does not affect DACDAT3 input to AIF1 or AIF2. Register 0322h AIF3DAC Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R803 (0323h) AIF3ADC Data 0 AIF3ADC_DAT_I NV 0 AIF3 Transmit Data Invert 0 = Not inverted 1 = Inverted Note that this controls the AIF3 Mono PCM interface path only; it does not affect ADCDAT3 output from AIF1 or AIF2. Register 0323h AIF3ADC Data REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1024 (0400h) AIF1 ADC1 Left Volume 8 AIF1ADC1_VU 0 AIF1ADC output path Volume Update Writing a 1 to this bit will cause the AIF1ADC1L and AIF1ADC1R volume to be updated simultaneously 7:0 AIF1ADC1L_VOL [7:0] 1100_0000 AIF1ADC (Left) output path Digital Volume 00h = MUTE 01h = -71.625dB … (0.375dB steps) EFh = +17.625dB Register 0400h AIF1 ADC1 Left Volume |
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