Pin Description

Pin No.

Pin Name

I/O

Description

1~4

SW0~SW3

I

4-bit general purpose input port

5DO

O

Output serial data at the falling edge of the shift clock,

starting from low order bit. This is an NMOS open-drain

output pin.

6DI

I

Input serial data at the rising edge of the shift clock, start-

ing from the low order bit.

7, 43

VSS

¾

Power supply, ground

8

CLK

I

Reads serial data at the rising edge, and outputs data at the

falling edge.

9CS

I

Initializes serial interface at the rising or falling edge of the

HT16512. Then it waits to receive a command. Data input

after CS has fallen is processed as a command. While com-

mand data is processed, current processing is stopped, and

the serial interface is initialized. While CS is high, CLK is

ignored.

10~13

K0~K3

I

Keying data input to these pins is latched at the end of the

display cycle.

14, 38

VDD

¾

Posistive power supply

15~20

S0/K0~S5/K5

O

Segment or key source output pins (dual function). This is

PMOS open-drain and pull-low resistor output.

21~25

S6~S10

O

Segment driver output pins (segment only). This is PMOS

open-drain and pull-low resistor output.

26, 28~31 S11/G10~S15/G6

O

Segment or Grid driver output pins. These pins are

selectable for segment or grid driving. This is PMOS

open-drain and pull-low resistor output.

27

VEE

¾

VFD power supply

37~32

G0~G5

O

Grid driver output pins (Grid only). This is PMOS

open-drain and pull-low resistor output.

42~39

LED0~LED3

O

LED driver output ports. This is a CMOS output pin.

44

OSC

I

Connected to an external resistor or an RC oscillator cir-

cuit.

HT16512

3

December 24, 1999