HT47C20L datasheet(18/55 Pages) HOLTEK

18 / 55 page

HT47C20L

January 18, 2000

The system can leave the halt mode by means of

an external reset, an interrupt, an external fall-

ing edge signal on port A or a WDT overflow. An

external reset causes a device initialization and

the WDT overflow performs a ²warm reset².Ex-

amining the TO and PD flags, the reason for

chip reset can be determined. The PD flag is

cleared when system power-up or executing the

CLR WDT instruction and is set when the HALT

instruction is executed. The TO flag is set if the

WDT time-out occurs, and causes a wake-up

that only resets the PC and SP, the others main-

tain their original status.

The port A wake-up and interrupt methods can

be considered as a continuation of normal execu-

tion. Each bit in port A can be independently se-

lected to wake up the device by mask option.

Awakening from an I/O port stimulus, the pro-

gram will resume execution of the next instruc-

tion. If awakening from an interrupt, two

sequences may happen. If the related interrupt is

disabled or the interrupt is enabled but the stack

is full, the program will resume execution at the

next instruction. If the interrupt is enabled and

the stack is not full, a regular interrupt response

takes place.

If an interrupt request flag is set to ²1² before en-

tering the halt mode the wake-up function of the

related interrupt will be disabled.

If the wake-up results from an interrupt acknowl-

edgment, the actual interrupt subroutine execution

will be delayed by more than one cycle. However, if

the wake-up results in the next instruction execu-

tion, the execution will be performed immediately.

To minimize power consumption, all the I/O pins

should be carefully managed before entering the

halt mode.

Reset

There are three ways in which a reset may occur.

· RES reset during normal operation

· RES reset during halt mode

· WDT time-out reset during normal operation

· The LVR is enable and the VDD is lower then

VLVR

The WDT time-out during halt mode is differ-

ent from other chip reset conditions, since it can

perform a warm reset that just resets the PC

and SP leaving the other circuits in their origi-

nal state. Some registers remain unchanged

during other reset conditions. Most registers

are reset to the ²initial condition² when the re-

set conditions are met. By examining the PD

and TO flags, the program can distinguish be-

tween different ²chip resets².

RESET Conditions

System power-up

RES reset or LVR reset during

normal operation

RES reset or LVR reset

wake-up from halt mode

WDT time-out during normal

operation

WDT wake-up from halt mode

Note: ²u² means ²unchanged²

To guarantee that the crystal oscillator has started

and stabilized, the SST (system start-up timer)

provides an extra delay of 8192 system clock

pulses when the system powers up.

HT47C20L Datasheet(PDF) 18 Page - Holtek Semiconductor Inc

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