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GMS81C50 Datasheet(PDF) 42 Page - Hynix Semiconductor |
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GMS81C50 Datasheet(HTML) 42 Page - Hynix Semiconductor |
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42 / 99 page  HYUNDAI GMS81C50 Series 39 10. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. Figure 10-1 Block Diagram of Clock Generator Prescaler consists of 12-bit binary counter. The clock sup- plied from oscillation circuit is input to prescaler (fex). The divided output from each bit of prescaler is provided to peripheral hardware. Figure 10-2 Block diagram of Prescaler PRESCALER C.P.G MUX WDT (6) COMPARATOR Internal Data Bus 01234 05 6 6 WDTON To Reset Circuit IFWDT WDTCL IFBIT 5 0 7 0 fcpu fex PS1 ENPCK Peripheral CKCTLR BTCL 3 8 OSC Circuit B.I.T (8) 6 WDTR Internal System Clock 5 B.I.T Peripheral PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 fex ENPCK fcpu PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 |
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