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GMS81C50 Datasheet(PDF) 71 Page - Hynix Semiconductor |
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GMS81C50 Datasheet(HTML) 71 Page - Hynix Semiconductor |
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71 / 99 page ![]() GMS81C50 Series HYUNDAI 68 Note : Whe n WD TR R e gis ter va lue i s 63 (3 F h) (Caution) : Do not use ``0`` for WDTR Register value. Device come into the reset state by WDT 32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us 0 -- WDTON ENPCK BTCL BTS2 BTS1 BTS0 7 W <00C7 h> CKCTLR Clock Control Register BTS0 WDT Input clock 0 1 BTS1 0 0 BTS2 0 0 Max. Interval of WDT Output (*note1) 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us |
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