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GMS90C51 Datasheet(PDF) 16 Page - Hynix Semiconductor |
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GMS90C51 Datasheet(HTML) 16 Page - Hynix Semiconductor |
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16 / 59 page ![]() GMS90 Series 12 Dec. 1998 Ver 3.0 CPU The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0 µs (40MHz: 300ns). Special Function Register PSW Reset value of PSW is 00H. Bit Function CY Carry Flag AC Auxiliary Carry Flag (for BCD operations) F0 General Purpose Flag RS1 0 0 1 1 RS0 0 1 0 1 Register Bank select control bits Bank 0 selected, data address 00H - 07H Bank 1 selected, data address 08H - 0FH Bank 2 selected, data address 10H - 17H Bank 3 selected, data address 18H - 1FH OV Overflow Flag F1 General Purpose Flag P Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 P 7 6 54 32 10 LSB MSB Bit No. Addr. D0H PSW |
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