HMS87C1102 datasheet(59/88 Pages) HYNIX

59 / 88 page

Apr. 2001 ver 1.0

HMS87C130XA/120XA/110XA

15.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted

or the interrupt latch is cleared to “0” by a reset or an in-

struction. Interrupt acceptance sequence requires 8 fOSC (2

µs at fXIN=4MHz) after the completion of the current in-

struction execution. The interrupt service task is terminat-

ed upon execution of an interrupt return instruction

[RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to “0”.

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 15-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

A interrupt request is not accepted until the I-flag is set to

“1” even if a requested interrupt has higher priority than

that of the current interrupt being serviced.

When nested interrupt service is required, the I-flag should

be set to “1” by “EI” instruction in the interrupt service

program. In this case, acceptable interrupt sources are se-

lectively enabled by the individual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program

counter and the program status word are automatically

saved on the stack, but accumulator and other registers are

not saved itself. These registers are saved by the software

if necessary. Also, when multiple interrupt services are

nested, it is necessary to avoid using the same data memory

area for saving registers.

V.L.

System clock

Address Bus

SP-1

SP-2

V.H.

New PC

V.L.

Data Bus

Not used

PCH

PCL

PSW

ADL

OP code

ADH

Instruction Fetch

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Basic Interval Timer

012H

0F3H

0FFE6H

0FFE7H

0EH

2FH

0F312H

0F313H

Entry Address

Correspondence between vector table address for BIT interrupt

and the entry address of the interrupt service program.

Vector Table Address

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