PCF8534A datasheet(36/52 Pages) NXP

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PCF8534A

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Product data sheet

Rev. 6 — 25 July 2011

36 of 52

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to 16 PCF8534As can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I2C-bus slave address (SA0).

When cascaded PCF8534A are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8534A of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 23).

Table 21.

Addressing cascaded PCF8534A

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100

000

011

102

113

004

015

106

117

210

008

019

1010

1111

0012

0113

1014

1115

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