2

ICS9148-53

Pin Descriptions

Notes:

1:

Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

2:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

VDD1

PWR

Ref (0:2), XTAL power supply, nominal 3.3V

2

REF0

OUT

14.318 MHz reference clock.

FS3

IN

Frequency select pin. Latched Input. Along with other FS pins determins the

CPU, SDRAM, PCI & AGP frewuencies.

3,9,16,22,27,

33,39,45

GND

PWR

Ground

4X1

IN

Crystal input, has internal load cap (33pF) and feedback

resistor from X2

5

X2

OUT

Crystal output, nominally 14.318MHz. Has internal load

cap (33pF)

6

VDD2

PWR

Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V

7

PCICLK_F

OUT

Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew

(CPU early) This is not affected by PCI_STOP#

IN

Frequency select pin. Latched Input. Along with other FS pins determins the

CPU, SDRAM, PCI & AGP frewuencies.

8

PCICLK0

OUT

PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)

IN

Frequency select pin. Latched Input

10, 11, 12, 13, 47

PCICLK(1:5)

OUT

PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)

14

VDD5

PWR

Supply for fixed PLL, 48MHz, AGP0

15

BUFFERIN

IN

Input pin for SDRAM buffers.

17

CPU_STOP#

IN

Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile

Mode, MODE=0)

SDRAM 11

OUT

SDRAM clock output

18

IN

Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,

MODE=0)

SDRAM 10

OUT

SDRAM clock output

28, 29, 31, 32, 34,

35,37,38

SDRAM (0:9)

OUT

SDRAM clock outputs.

20

AGP_STOP#

1

IN

This asynchronous input halts AGP(1:2) clocks at logic "0" level when input

low (in Mobile Mode, MODE=0) Does not affect AGP0

SDRAM9

OUT

SDRAM clock output

21

PD#

1

IN

This asyncheronous Power Down input Stops the VCO, crystal & internal

clocks when active, Low. (In Mobile Mode, MODE=0)

SDRAM8

OUT

SDRAM clock output

19,30,36

VDD3

PWR

Supply for SDRAM (0:11), CPU Core, 48MHz clocks,

nominal 3.3V.

23

SDATA

IN

24

SCLK

IN

25

AGP0

OUT

Advanced Graphic Port output, powered by VDD4. Not affected by

AGP_STOP#

IN

Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.

Latched Input.

26

48MHz

OUT

48MHz output clock for USB timing.

IN

Frequency select pin. Latched Input. Along with other FS pins determins the

CPU, SDRAM, PCI & AGP frewuencies.

41, 43, 44

CPUCLK(0:3)

OUT

CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low

40

SDRAM12

OUT

Feedback SDRAM clock output.

42

VDDL

PWR

Supply for CPU (0:3), either 2.5V or 3.3V nominal

46

AGP1

OUT

Advanced Graphic Port output powered by VDD4.

48

VDD4

PWR

Supply for AGP (0:2)