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ICS9148-53 Datasheet(PDF) 7 Page - Integrated Circuit Systems

Part # ICS9148-53
Description  Frequency Generator & Integrated Buffers for Mother Boards
PDF  18 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9148-53 Datasheet(HTML) 7 Page - Integrated Circuit Systems

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ICS9148-53
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
B it
Pin #
PW D
D e s cription
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
40
1
S DRA M 12 (A ct/Inact)
Bit 3
-
1
(Reserved)
Bit 2
41
1
C P U C LK 2 (Act/Inact)
Bit 1
43
1
C P U C LK 1 (Act/Inact)
Bit 0
44
1
C P U C LK 0 (Act/Inact)
B it
Pin #
PWD
D e s cription
Bit 7
-
1
(Reserved)
Bit 6
7
1
P C IC LK _F (A ct/Inact)
Bit 5
-
1
(Reserved)
Bit 4
13
1
P C IC LK 4 (A ct/Inact)
Bit 3
12
1
P C IC LK 3 (A ct/Inact)
Bit 2
11
1
P C IC LK 2 (A ct/Inact)
Bit 1
10
1
P C IC LK 1 (A ct/Inact)
Bit 0
8
1
P C IC LK 0(A ct/Inact)
Bit
Pin #
PWD
Description
Bit 7
28
1
SDRAM7 (Act/Inact)
Bit 6
29
1
SDRAM6 (Act/Inact)
Bit 5
31
1
SDRAM5 (Act/Inact)
Bit 4
32
1
SDRAM4 (Act/Inact)
Bit 3
34
1
SDRAM3 (Act/Inact)
Bit 2
35
1
SDRAM2 (Act/Inact)
Bit 1
37
1
SDRAM1 (Act/Inact)
Bit 0
38
1
SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
B it
Pin #
PWD
D e s cription
Bit 7
25
1
AGP0 (Active/Inactive)
Bit 6
-
1
(Reserved)
Bit 5
26
-
FS0#
Bit 4
-
1
(Reserved)
Bit 3
17
1
SDRAM 11 (Act/Inact)
(Desktop M ode O nly)
Bit 2
18
1
SDRAM 10 (Act/Inact)
(Desktop M ode O nly)
Bit 1
20
1
SDRAM 9 (Act/Inact)
Bit 0
21
1
SDRAM 8 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
8
-
FS2#
Bit 5
7
-
FS1#
Bit 4
47
1
PCICLK5 (Act/Inact)
Bit 3
-
1
(Reserved)
Bit 2
2
-
FS3#
Bit 1
46
1
AGP1 (Act/Inact)
Bit 0
2
1
REF0 (Act/Inact)
Byte 2: PCIActive/Inactive Register
(1 = enable, 0 = disable)
Byte 6: Optional Register for Possible
Furture Requirements
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for futue
applications.
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
-
1
(Reserved)
Bit 0
-
1
(Reserved)



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