Integrated

Circuit

Systems, Inc.

General Description

Features

ICS9148-53

Block Diagram

Pentium is a trademark of Intel Corporation

I

Frequency Generator & Integrated Buffers for Mother Boards

9148-53 Rev C 08/14/98

Pin Configuration

48-Pin SSOP

Power Groups

VDD1=REF(0:1),X1,X2

VDD2=PCICLK_F,PCICLK(0:5)

VDD3 = SDRAM (0:12), supply for PLL core

VDD4=AGP(1:2)

VDD5=FixedPLL,48MHz,AGP0

VDDL= CPUCLK(0:3)

* Internal Pull-up Resistor of

240K to 3.3V on indicated inputs

The ICS9148-53 generates all clocks required for high speed

RISC or CISC microprocessor systems such as Intel

PentiumPro, AMD or Cyrix. Sixteen different reference

frequency multiplying factors are externally selectable with

smooth frequency transitions.

Spread spectrum may be enabled through I2C programming.

Spread spectrum typically reduces system EMI by 8dB to

10dB. This simplifies EMI qualification without resorting to

board design iterations or costly shielding. The ICS9148-53

employs a proprietary closed loop design, which tightly

controls the percentage of spreading over process and

temperature variations.

stop clock programming and frequency selection. The

SDRAM12 output may be used as a feed back into an off chip

PLL.

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Generates the following system clocks:

-3CPU(2.5V/3.3V)upto150MHz.

- 7 PCI(3.3V) (including one free

running PCICLK)

-2AGP(3.3V)@2x PCI

- 13 SDRAMs(3.3V) up to 150MHz

-1REF(3.3V)@14.318MHz

- 1 Fixed clock 3.3V @ 48MHz

•

Skew characteristics:

- CPU – CPU<250ps

- CPU(early) – PCI : 1-4ns

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programming for Power Management, Frequency Select

•

Efficient Power management scheme through power

down CPU, PCI,AGPand CPU_STOPclocks.

•

Uses external 14.318MHz crystal

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48pin300milSSOP.

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ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.