ICS9148-53 datasheet(5/18 Pages) ICST

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ICS9148-53

General I

2C serial interface information

For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with

an acknoledge bit between each byte.

The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set

R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the

address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I2C interface, the protocol is set to use only "Block Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those

two bytes. The data is loaded until a Stop sequence is issued.

The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running,

except in Tristate Mode.

At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1

(Enabled output state).

Then Byte 0, 1, 2, etc in

sequence until STOP.

Clock Generator

Address (7 bits)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

D2(H)

Then Byte 0, 1, 2, etc. in

sequence until STOP.

Clock Generator

Address (7 bits)

ACK

Byte Count

Readback

ACK

A(6:0) & R/W#

D3(H)

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