28F010 datasheet(9/30 Pages) INTEL

9 / 30 page

28F010

Read Command

While VPP is high for erasure and programming

memory contents can be accessed via the read

command The read operation is initiated by writing

00H into the command register

Microprocessor

read cycles retrieve array data The device remains

enabled for reads until the command register con-

tents are altered

The default contents of the register upon VPP pow-

er-up is 00H This default value ensures that no spu-

rious alteration of memory contents occurs during

the VPP power transition Where the VPP supply is

hard-wired to the 28F010 the device powers-up and

remains enabled for reads until the command-regis-

ter contents are changed Refer to the AC Read

Characteristics and Waveforms for specific timing

parameters

Intelligent Identifier Command

Flash memories are intended for use in applications

where the local CPU alters memory contents As

such manufacturer- and device-codes must be ac-

cessible while the device resides in the target sys-

tem PROM programmers typically access signature

codes by raising A9 to a high voltage However mul-

tiplexing high voltage onto address lines is not a de-

sired system-design practice

The 28F010 contains an Intelligent Identifier opera-

tion to supplement traditional PROM-programming

methodology The operation is initiated by writing

90H into the command register Following the com-

mand write a read cycle from address 0000H re-

trieves the manufacturer code of 89H A read cycle

from address 0001H returns the device code of

B4H To terminate the operation it is necessary to

write another valid command into the register

Set-up EraseErase Commands

Set-up Erase is a command-only operation that

stages the device for electrical erasure of all bytes in

the array The set-up erase operation is performed

by writing 20H to the command register

To commence chip-erasure the erase command

(20H) must again be written to the register The

erase operation begins with the rising edge of the

pulse and terminates with the rising edge of

the next WE

pulse (ie Erase-Verify Command)

This two-step sequence of set-up followed by execu-

tion ensures that memory contents are not acciden-

tally erased Also chip-erasure can only occur when

high voltage is applied to the VPP pin In the absence

of this high voltage memory contents are protected

against erasure Refer to AC Erase Characteristics

and Waveforms for specific timing parameters

Erase-Verify Command

The erase command erases all bytes of the array in

parallel After each erase operation all bytes must

be verified The erase verify operation is initiated by

writing A0H into the command register The address

for the byte to be verified must be supplied as it is

latched on the falling edge of the WE

pulse The

rising edge of its WE

pulse

The 28F010 applies an internally-generated margin

voltage to the addressed byte Reading FFH from

the addressed byte indicates that all bits in the byte

are erased

The erase-verify command must be written to the

command register prior to each byte verification to

latch its address The process continues for each

byte in the array until a byte does not return FFH

data or the last address is accessed

In the case where the data read is not FFH another

erase operation is performed

(Refer to Set-up

EraseErase) Verification then resumes from the

address of the last-verified byte Once all bytes in

the array have been verified the erase step is com-

plete The device can be programmed At this point

the verify operation is terminated by writing a valid

command (eg Program Set-up) to the command

trates how commands and bus operations are com-

bined to perform electrical erasure of the 28F010

Refer to AC Erase Characteristics and Waveforms

for specific timing parameters

Set-up ProgramProgram Commands

Set-up program is a command-only operation that

stages the device for byte programming Writing 40H

into the command register performs the set-up

operation

Once the program set-up operation is performed

the next WE

pulse causes a transition to an active

programming operation

Addresses are internally

latched on the falling edge of the WE

pulse Data

is internally latched on the rising edge of the WE

pulse The rising edge of WE

also begins the pro-

gramming operation The programming operation

terminates with the next rising edge of WE

used

to write the program-verify command Refer to AC

Programming Characteristics and Waveforms for

specific timing parameters

28F010 Datasheet(PDF) 9 Page - Intel Corporation

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