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28F020 Datasheet(PDF) 15 Page - Intel Corporation |
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28F020 Datasheet(HTML) 15 Page - Intel Corporation |
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15 / 38 page ![]() E 28F020 15 Start Erasure (4) Data = 00H? Program All Bytes to 00H Apply V PPH (1) ADDR = 00H PLSCNT = 0 Time Out 10 ms Time Out 6 µs Read Data from Device Data = FFH? Inc PLSCNT = 1000? Last Address? Erasure Completed Erase Error Write Erase Set-Up Cmd Write Erase Cmd Write Read Cmd Apply V PPL (1) Apply V PPL (1) Write Erase Verify Cmd Increment Addr Y Bus Operation Comments Entire Memory Must = 00H Before Erasure Use Quick-Pulse Programming Algorithm (Figure 4) Standby Wait for V PP Ramp to VPPH (1) Initialize Addresses and Pulse-Count Write Data = 20H Write Data = 20H Stand-by Duration of Erase Operation (t WHWH2 ) Write Addr = Byte to Verify; Data = A0H; Stops Erase Operation(3) Standby t WHGL Read Read Byte to Verify Erasure Standby Compare Output to FFH Increment Pulse-Count Standby Wait for V PP Ramp to VPPL (1) N Y N N N Y Y Command Set-Up Erase Erase Erase (2) Verify Write Data = 00H, Resets the Register for Read Operations Read 0245_05 NOTES: 1. See DC Characteristics for the value of VPPH and VPPL. 2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is written with the Read command. 3. Refer of Principles of Operation. 4. Caution: The algorithm must be followed to ensure proper and reliable operation of the device. Figure 5. 28F020 Quick-Erase Algorithm |
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