80296SA datasheet(12/40 Pages) INTEL

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PRELIMINARY

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

EXTINT3:0

External Interrupts

These programmable interrupts are controlled by the EXTINT_CON register. This

whether a rising edge/high level or falling edge/low level activates the interrupt.

In standby and powerdown modes, asserting the EXTINT

x signal causes the device

to resume normal operation. The interrupt does not need to be enabled, but the pin

must be configured as a special-function input. If the EXTINT

x interrupt is enabled,

the CPU executes the interrupt service routine. Otherwise, the CPU executes the

instruction that immediately follows the command that invoked the power-saving

mode.

In idle mode, asserting any enabled interrupt causes the device to resume normal

operation.

EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with

P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package pin

with P3.7.

HLDA#

Bus Hold Acknowledge

This active-low output indicates that the CPU has released the bus as the result of

an external device asserting HOLD#. When the bus-hold protocol is enabled

(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the

configuration selected through the port configuration registers (P2_MODE, P2_DIR,

and P2_REG). An attempt to change the pin configuration is ignored until the bus-

hold protocol is disabled (WSR.7 is cleared).

HLDA# shares a package pin with P2.6.

HOLD#

Bus Hold Request

An external device uses this active-low input signal to request control of the bus.

When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can

function only as HOLD#, regardless of the configuration selected through the port

configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change

the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is

cleared).

HOLD# shares a package pin with P2.5.

INST

Instruction Fetch

When high, INST indicates that an instruction is being fetched from external

memory. The signal remains high during the entire bus cycle of an external

instruction fetch. INST is low for data accesses, including interrupt vector fetches

and chip configuration byte reads. INST is low during internal memory fetches.

Table 4. Signal Descriptions (Continued)

Name

Type

Description

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