80296SA datasheet(28/40 Pages) INTEL

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PRELIMINARY

80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

6.2.4

AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE

Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.

Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode

Symbol

Parameter

Min

Max

Units

XTAL

Frequency on XTAL1, PLL in 1x mode

50 (1)

MHz

Frequency on XTAL1, PLL in 2x mode

8 (2)

MHz

Frequency on XTAL1, PLL in 4x mode

8 (2)

12.5

MHz

Operating frequency, f = F

XTAL

1; PLL in 1x mode

MHz

Operating frequency, f = 2F

XTAL

1; PLL in 2x mode

Operating frequency, f = 4F

XTAL

1; PLL in 4x mode

Period, t = 1/f

62.5

AVWL

Address Valid to WR# Falling Edge

t – 10

AVRL

Address Valid to RD# Falling Edge

t – 10

RHRL

Read High to Next Read Low

t – 5

XHCH

XTAL1 High to CLKOUT High or Low

CLCL

CLKOUT Cycle Time

CHCL

CLKOUT High Period

t – 10

t + 15

CLLH

CLKOUT Falling Edge to ALE Rising Edge

–13

LLCH

ALE Falling Edge to CLKOUT Rising Edge

–15

LHLH

ALE Cycle Time

ns (3,4)

LHLL

ALE High Period

t – 10

t + 10

RLCL

RD# Low to CLKOUT Falling Edge

–5

RLRH

RD# Low Period

3t – 18

ns (3)

RHLH

RD# Rising Edge to ALE Rising Edge

t – 4

t + 15

ns (4)

WLCL

WR# Low to CLKOUT Falling Edge

–8

QVWH

Data Stable to WR# Rising Edge

3t – 10

ns (4)

CHWH

CLKOUT High to WR# Rising Edge

–11

WLWH

WR# Low Period

3t – 10

ns (3)

WHQX

Data Hold after WR# Rising Edge

t – 5

t + 20

WHLH

WR# Rising Edge to ALE Rising Edge

t – 5

t + 10

ns (3)

NOTES:

25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

If using either READY or BUSCON

x to insert wait states, add 2t

× n, where n = number of wait states.

Assuming back-to-back bus cycles.

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