80296SA datasheet(25/40 Pages) INTEL

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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

WHQX

Data Hold after WR# Rising Edge

t – 7

WHLH

WR# Rising Edge to ALE Rising Edge

t – 15

t + 20

WHBX

BHE#, INST Hold after WR# Rising Edge

WHAX

AD15:8 Hold after WR# Rising Edge

t – 4

ns (5)

RHBX

BHE#, INST Hold after RD# Rising Edge

RHAX

AD15:8 Hold after RD# Rising Edge

t – 4

ns (5)

TWHSH

A19:16, CS# Hold after WR# Rising Edge

RHSH

A19:16, CS# Hold after RD# Rising Edge

Table 9. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode

Symbol

Parameter

Min

Max

Units

AVDV

AD15:0 Valid to Input Data Valid

3t – 32

ns (1, 2)

RLDV

RD# Active to Input Data Valid

2t – 40

ns (1, 2)

SLDV

Chip Select Low to Data Valid

4t – 28

ns (1, 2)

CHDV

CLKOUT High to Input Data Valid

2t – 25

RHDZ

End of RD# to Input Data Float

t – 3

ns (2)

RXDX

Data Hold after RD# Inactive

AVYV

AD15:0 Valid to READY (Inactive) Setup

2t – 42

ns (3)

1YX

First READY Hold (active) after CLKOUT High

t – 4

2t – 21

ns (4, 5)

2YX

Non-first READY Hold (active) after CLKOUT High

2t – 21

ns (4)

YLYH

Non-READY (Inactive) Time

No Upper

Limit

NOTES:

If using the READY signal to insert wait states, you must program at least one wait state in the

BUSCON

x register because the first falling edge of READY is not synchronized with a CLKOUT edge.

If using the BUSCON

x register without the READY signal to insert wait states, add 2t

× n, where n =

number of wait states.

If using the BUSCON

x register to insert wait states, add 2t

× (n–1), where n = number of wait states.

Exceeding the maximum specification causes additional wait states.

If you program two or more wait states in the BUSCON

x register, the T

1YX minimum does not apply.

Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode (Continued)

Symbol

Parameter

Min

Max

Units

NOTES:

25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz

can be applied with an external clock source.

When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8

MHz. The PLL cannot be run at frequencies lower than 16 MHz.

If wait states are used, add 2t

× n, where n = number of wait states.

Assuming back-to-back bus cycles.

8-bit bus only.

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