Data Sheet

AD5253/AD5254

Rev. C | Page 15 of 32

From Master to Slave

From Slave to Master

S = start condition

P = stop condition

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

R/W= read enable bit at logic high; write enable bit at logic low

CMD/REG = command enable bit at logic high; register access bit at logic low

EE/RDAC = EEMEM register at logic high; RDAC register at logic low

A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses

0 WRITE

S

0

1

0

1

1

A

D

1

A

D

0

0

A

A

4

A

3

A

2

A

1

A

0

A

P

DATA

0

(1 BYTE +

ACKNOWLEDGE)

SLAVE ADDRESS

INSTRUCTIONS

AND ADDRESS

CMD/

REG

EE/

RDAC

0 REG

A/

A

Figure 27. Single Write Mode

0 WRITE

S

0

1

0

1

1

A

D

1

A

D

0

0

A

A

4

A

3

A

2

A

1

A

0

P

A

A

RDAC_N

DATA

RDAC_N + 1

DATA

0

(N BYTE +

ACKNOWLEDGE)

SLAVE ADDRESS

INSTRUCTIONS

AND ADDRESS

CMD/

REG

EE/

RDAC

0 REG

A/

A

Figure 28. Consecutive Write Mode

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)

A4

A3

A2

A1

A0

RDAC

Data Byte Description

0

0

0

0

0

RDAC0

6-/8-bit wiper setting (2 MSB of AD5253 are X)

0

0

0

0

1

RDAC1

6-/8-bit wiper setting (2 MSB of AD5253 are X)

0

0

0

1

0

RDAC2

6-/8-bit wiper setting (2 MSB of AD5253 are X)

0

0

0

1

1

RDAC3

6-/8-bit wiper setting (2 MSB of AD5253 are X)

0

0

1

0

0

Reserved

:

:

:

:

:

:

:

:

:

:

:

:

0

1

1

1

1

Reserved