AD5253 datasheet(18/32 Pages) AD

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AD5253/AD5254

Data Sheet

Rev. C | Page 18 of 32

RDAC/EEMEM Quick Commands

The AD5253/AD5254 feature 12 quick commands that facilitate

easy manipulation of RDAC wiper settings and provide RDAC-

to-EEMEM storing and restoring functions. The command

format is shown in Figure 31, and the command descriptions

are shown in Table 9.

When using a quick command, issuing a third byte is not

needed, but is allowed. The quick commands reset and store

RDAC to EEMEM require acknowledge polling to determine

whether the command has finished executing.

RAB Tolerance Stored in Read-Only Memory

The AD5253/AD5254 feature patented RAB tolerances storage in

the nonvolatile memory. The tolerance of each channel is stored

in the memory during the factory production and can be read

by users at any time. The knowledge of the stored tolerance,

which is the average of RAB over all codes (see Figure 16), allows

users to predict RAB accurately. This feature is valuable for

precision, rheostat mode, and open-loop applications, in which

knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory and are

expressed as percentages. Each tolerance is 16 bits long and is

stored in two memory locations (see Table 10). The tolerance

data is expressed in sign magnitude binary format stored in two

bytes; an example is shown in Figure 32 . For the first byte in

and the 7 LSB is designated for the integer portion of the

tolerance. For the second byte in Register N + 1, all eight data

bits are designated for the decimal portion of tolerance. As

shown in Table 10 and Figure 32, for example, if the rated RAB is

10 kΩ and the data readback from Address 11000 shows 0001

1100 and Address 11001 shows 0000 1111, then RDAC0

tolerance can be calculated as

MSB: 0 = +

Next 7 MSB: 001 1100 = 28

8 LSB: 0000 1111 = 15 × 2–8 = 0.06

Tolerance = 28.06% and, therefore,

RAB_ACTUAL = 12.806 kΩ

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal

write cycle begins. The I2C interface of the device is disabled. To

determine if the internal write cycle is complete and the I2C

interface is enabled, interface polling can be executed. I2C

interface polling can be conducted by sending a start condition

followed by the slave address and the write bit. If the I2C

interface responds with an ACK, the write cycle is complete and

the interface is ready to proceed with further operations. Other-

wise, I2C interface polling can be repeated until it succeeds.

Command 2 and Command 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to logic low after EEMEM programming

protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read

operations function as normal.

Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)

Command Description

NOP

Restore EEMEM (A1, A0) to RDAC (A1, A0)1

Store RDAC (A1, A0) to EEMEM (A1, A0)

Decrement RDAC (A1, A0) 6 dB

Decrement all RDACs 6 dB

Decrement RDAC (A1, A0) one step

Decrement all RDACs one step

Reset: restore EEMEMs to all RDACs

Increment RDACs (A1, A0) 6 dB

Increment all RDACs 6 dB

Increment RDACs (A1, A0) one step

Increment all RDACs one step

Reserved

1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

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