AD5253 datasheet(20/32 Pages) AD

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AD5253/AD5254

Data Sheet

Rev. C | Page 20 of 32

I2C-COMPATIBLE 2-WIRE SERIAL BUS

SDA

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

SCL

ACK. BY

AD525x

ACK. BY

AD525x

ACK. BY

AD525x

FRAME 1

DATA BYTE

STOP BY

MASTER

START BY

MASTER

AD1 AD0 R/W

Figure 33. General I2C Write Pattern

SDA

FRAME1

SLAVE ADDRESS BYTE

FRAME 2

RDAC REGISTER

SCL

ACK. BY

AD525x

NO ACK. BY

MASTER

STOP BY

MASTER

START BY

MASTER

AD1 AD0

R/W

Figure 34. General I2C Read Pattern

The first byte of the AD5253/AD5254 is a slave address byte

(see Figure 33 and Figure 34). It has a 7-bit slave address and an

R/W bit. The 5 MSB of the slave address is 01011, and the next

2 LSB is determined by the states of the AD1 and AD0 pins.

AD1 and AD0 allow the user to place up to four

AD5253/AD5254 devices on one bus.

AD5253/AD5254 can be controlled via an I2C-compatible serial

bus and are connected to this bus as slave devices. The 2-wire

I2C serial bus protocol (see Figure 33 and Figure 34) follows:

1. The master initiates a data transfer by establishing a start

condition, such that SDA goes from high to low while SCL

is high (see Figure 33). The following byte is the slave

address byte, which consists of the 5 MSB of a slave address

defined as 01011. The next two bits are AD1 and AD0, I2C

device address bits. Depending on the states of their AD1

and AD0 bits, four AD5253/AD5254 devices can be

addressed on the same bus. The last LSB, the R/W bit,

determines whether data is read from or written to the

slave device.

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is called an acknowledge bit). At

this stage, all other devices on the bus remain idle while

the selected device waits for data to be written to or read

from its serial register.

2. In the write mode (except when restoring EEMEM to the

RDAC register), there is an instruction byte that follows

the slave address byte. The MSB of the instruction byte is

labeled CMD/REG. MSB = 1 enables CMD, the command

instruction byte; MSB = 0 enables general register writing.

The third MSB in the instruction byte, labeled EE/RDAC,

is true when MSB = 0 or when the device is in general

writing mode. EE enables the EEMEM register, and REG

enables the RDAC register. The 5 LSB, A4 to A0, designates

the addresses of the EEMEM and RDAC registers (see

Figure 27 and Figure 28). When MSB = 1 or when the

device is in CMD mode, the four bits following the MSB

are C3 to C1, which correspond to 12 predefined EEMEM

controls and quick commands; there are also four factory-

reserved commands. The 3 LSB—A2, A1, and A0—are 4-

channel RDAC addresses (see Figure 31). After

acknowledging the instruction byte, the last byte in the

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Figure 33).

3. In current read mode, the RDAC0 data byte immediately

follows the acknowledgment of the slave address byte.

After an acknowledgement, RDAC1 follows, then RDAC2,

and so on. (There is a slight difference in write mode,

where the last eight data bits representing RDAC3 data are

followed by a no acknowledge bit.) Similarly, the

transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of

SCL (see Figure 34). Another reading method, random

read method, is shown in Figure 30.

4. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is

defined as a low-to-high transition on the SDA line that

occurs while SCL is high. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition (see Figure 33). In read mode, the master

issues a no acknowledge for the ninth clock pulse, that is,

the SDA line remains high. The master brings the SDA line

low before the 10th clock pulse and then brings the SDA

line high to establish a stop condition (see Figure 34).

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