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AS87196CB Datasheet(PDF) 16 Page - Intel Corporation

Part # AS87196CB
Description  ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0
PDF  33 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

AS87196CB Datasheet(HTML) 16 Page - Intel Corporation

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87C196CA87C196CB
AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 87C196CACB will meet these specifications
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL1
40
20
MHz(1)
TOSC
XTAL1 Period (1FXTAL)
500
250
ns
TXHCH
XTAL1 High to CLKOUT High or Low
a
20
110
ns
TOFD
Clock Failure to Reset Pulled Low(6)
440
m
s
TCLCL
CLKOUT Period
2 TOSC
ns
TCHCL
CLKOUT High Period
TOSC b 10
TOSC a 15
ns
TCLLH
CLKOUT Low to ALEADV High
b
15
a
10
ns
TLLCH
ALEADV Low to CLKOUT High
b
20
a
15
ns
TLHLH
ALEADV Cycle Time
4 TOSC
ns(5)
TLHLL
ALEADV High Time
TOSC b 10
TOSC a 10
ns
TAVLL
Address Valid to ALE Low
TOSC b 15
ns
TLLAX
Address Hold After ALEADV Low
TOSC b 40
ns
TLLRL
ALEADV Low to RD Low
TOSC b 30
ns
TRLCL
RD Low to CLKOUT Low
CA
a
4
a
30
ns
CB
b
8
a
20
ns
TRLRH
RD Low Period
TOSC b 10
ns(5)
TRHLH
RD High to ALEADV High
TOSC
TOSC a 25
ns(3)
TRLAZ
RD Low to Address Float
5
ns
TLLWL
ALEADV Low to WR Low
TOSC b 10
ns
TCLWL
CLKOUT Low to WR Low
b
5
a
25
ns
TQVWH
Data Valid before WR High
TOSC b 23
ns
TCHWH
CLKOUT High to WR High
b
10
a
15
ns
TWLWH
WR Low Period
CB
TOSC b 30
ns(5)
CA
TOSC b 20
TWHQX
Data Hold after WR High
TOSC b 25
ns
TWHLH
WR High to ALEADV High
TOSC b 10
TOSC a 15
ns(3)
TWHBX
BHE INST Hold after WR High
TOSC b 10
ns
TWHAX
AD8 – 15 Hold after WR High
TOSC b 30
ns(4)
TRHBX
BHE INST Hold after RD High
TOSC b 10
ns
TRHAX
AD8 – 15 Hold after RD High
TOSC b 30
ns(4)
NOTES
1 Testing performed at 40 MHz however the device is static by design and will typically operate below 1 Hz
2 Typical specifications not guaranteed
3 Assuming back-to-back bus cycles
4 8-bit bus only
5 If wait states are used add 2 Tosc c n where n e number of wait states If mode 0 (1 automatic wait state added)
operation is selected add 2 TOSC to specification
6 TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H Programming the CDE bit enables oscillator fail detec-
tion
16



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